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3
VOTE
Not supported for the current status
Status Planned for future release
Workspace Spectrum LSF
Components Scheduling
Created by Guest
Created on Oct 2, 2024

RELATED IDEAS

Merged idea
This idea has been merged into another idea. To comment or vote on this idea, please visit SPCLSF-I-1779 Consider AMD ccd/l3 cache in affinity string.

Affinity scheduling must take L3 cache hierarchy into account Merged

Newer CPUs have multiple L3 caches, with dedicated cores per L3 cache. Running multi-threaded jobs on all cores within a shared L3 cache can reduce runtime in our cases up 70%, compared to running over multiple L3 caches. Think of the AMD EPYC 9354 processor.

Needed By Quarter
  • Admin
    Bill McMillan
    Jan 25, 2026

    As discussed, the hope was to deliver this in 2025, but it was pre-empted for resource by another project.

    The legacy/unix (sgi, hp, sun) definition of numa follows host->numa->socket->core
    For Genoa/Turin etc, this as been flipped to host->socket->numa->L3cache->core

    Your workaround of setting HWLOC_SYNTHETIC to make each L3/CCD look like a numa is good, but as you say, it will sometimes not give the desired result.

    This work is in plan for this year, and will allow affinity(L3cache) to ensure all cores are allocated from the same L3 cache

    Reply
  • Guest
    Jan 19, 2026

    Hi, do you already have an update? Will the scheduling also take the available places into account for selecting the optimal execution node?

    Reply
  • Guest
    Oct 8, 2024

    Thanks! Can you share more details?

    Reply
  • Admin
    Bill McMillan
    Oct 7, 2024

    This is something that is on our roadmap, with a tentative 2025 delivery.

    Reply

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